Power Delivery & PCB Design

A real capacitor is modeled as: C (ideal capacitance) in series with ESR (equivalent series resistance) and ESL (equivalent series inductance), with a parallel leakage resistance.

The impedance follows a V-shape vs. frequency: capacitive below SRF, minimum at SRF (where Z ≈ ESR), then inductive above SRF. Different capacitor values have different SRFs.

Using multiple values in parallel (e.g., 10pF + 100nF + 10µF) creates a low-impedance path across a wide frequency range, with each cap covering a different band of the PDN impedance profile.

Mechanisms:

• Capacitive (electric field) coupling: Fast voltage edges couple through parasitic capacitance between traces.
• Inductive (magnetic field) coupling: Current loops create mutual inductance.
• Common-impedance coupling: Shared return paths (ground plane) carry both digital and RF currents.
• Radiated EMI: The digital line acts as an unintentional antenna.

Mitigation: Maximize separation, use ground guard traces, route on different layers with orthogonal orientation, ensure continuous ground plane between them, add filtering on the GPIO, and consider shielding or isolation slots with via stitching.

The return current on the ground plane must flow around the slot, creating a large current loop. This causes:

• Increased inductance in the return path, changing the characteristic impedance and causing reflections.
• EMI radiation from the enlarged current loop acting as a slot antenna.
• Crosstalk to other signals whose return currents also detour around the slot.
• Signal integrity degradation: impedance discontinuity, increased insertion loss, and potential resonance.

Rule: Never let an RF signal cross a ground plane discontinuity.

Choose the LDO. A VCO is extremely sensitive to power supply noise — any ripple on V_DD directly modulates the output frequency, creating spurious tones and degrading phase noise. Switching regulators generate significant ripple and EMI at their switching frequency and harmonics. An LDO provides a clean, low-noise supply with high PSRR. The efficiency penalty is acceptable because VCOs typically draw modest current.

Star topology prevents common-impedance coupling between blocks. In a daisy-chain, the PA’s large current transients flow through the same trace impedance that feeds the LNA, modulating the LNA’s supply voltage and injecting noise/distortion.

With star topology, each block has its own dedicated trace back to the common point, so one block’s current draw doesn’t create voltage drops that affect others. This maintains isolation between sensitive (LNA) and noisy (PA) blocks.

DCR (DC Resistance): Causes I²R power loss, directly affecting efficiency and generating heat. Lower DCR requires larger wire/core → bigger footprint.

AC Losses: Core losses (hysteresis + eddy current) and winding AC resistance (skin/proximity effect). These increase with frequency and ripple current.

Trade-offs:

• Size vs. DCR: Smaller inductors have higher DCR and more heat.
• Inductance value: Higher L → lower ripple current → lower AC core loss, but larger footprint and slower transient response.
• Core material: Ferrite has low core loss but saturates at lower current; powdered iron handles higher current but has more loss.
• Shielding: Shielded inductors reduce EMI but are larger.
• Saturation current: Must exceed peak inductor current with margin.

At GHz frequencies, the skin effect confines current flow to a thin layer near the conductor surface. The skin depth in copper at 1GHz is only ~2µm, dramatically reducing the effective cross-section and increasing resistance. Additionally, surface roughness (comparable to skin depth at GHz) forces current to travel a longer path.

For power delivery, this means PDN traces that appear low-impedance at DC may present significant impedance at RF frequencies, degrading high-frequency decoupling effectiveness. Proper high-frequency decoupling capacitors placed close to the IC pins are critical.

Via parasitics:

• Inductance: Each via adds ~0.5–1nH of series inductance, increasing impedance at high frequencies.
• Resistance: Finite conductivity adds series resistance.
• Capacitance: Via barrel-to-plane capacitance (usually small, ~tens of fF).

Impact: Via inductance in series with a decoupling cap raises the effective SRF and adds impedance. A 100pF cap with 1nH via inductance resonates at ~500MHz instead of its intrinsic SRF.

Mitigation: Use multiple vias in parallel, minimize via length (blind/buried vias), place caps on the same layer as the IC pad, use via-in-pad technology, and keep via-to-pad connections as short as possible.