Data Converters & Sampling

Data Converters & Sampling

ADC architectures, Nyquist criterion, INL/DNL, sample-and-hold circuits, and performance metrics.

Explain SAR, Delta-Sigma, and Flash ADCs. When would you use each?
  • SAR (Successive Approximation): Uses a binary search algorithm with a DAC and comparator. Medium speed (1–10 MSPS), medium resolution (8–18 bits), low power. Best for: sensor interfaces, data acquisition, multiplexed inputs.
  • Delta-Sigma (ΔΣ): Oversamples and uses noise shaping to push quantization noise out of band. Very high resolution (16–24+ bits), lower speed. Best for: audio, precision measurements, weigh scales.
  • Flash: Uses 2^N−1 comparators in parallel for N-bit resolution. Extremely fast (GHz+), low resolution (4–8 bits), high power. Best for: oscilloscopes, radar, high-speed communications.
Nyquist criterion: digitizing a 100kHz signal — what sampling rate and why?
The Nyquist theorem requires sampling at >2× the signal bandwidth: f_s > 200kHz minimum.

In practice, sample at 2.5–5× (250–500kHz) to allow for a realizable anti-aliasing filter with finite roll-off. The guard band between the signal bandwidth and f_s/2 determines how steep (and expensive) the anti-aliasing filter must be.

INL/DNL: explain positive DNL, negative DNL, and missing codes.
DNL (Differential Nonlinearity): Deviation of each code width from the ideal 1 LSB.

  • Positive DNL: A code step wider than 1 LSB — the transfer function step is too wide.
  • Negative DNL: A code step narrower than 1 LSB.
  • DNL = −1 LSB: The code width is zero → missing code. The ADC skips that output value entirely.

INL (Integral Nonlinearity): Cumulative sum of DNL errors; measures overall deviation of the transfer function from the ideal straight line. Large INL causes harmonic distortion and degrades SFDR.

Sample-and-hold: calculate acquisition time for 0.1% accuracy.
The S/H capacitor charges through the switch resistance with time constant τ = R_sw × C. To settle to 0.1% accuracy (within 0.001 of final value):

e^(−t/τ) = 0.001 → t = τ × ln(1000) ≈ 6.9τ

For example, with R_sw = 100Ω and C = 10pF: τ = 1ns, so t_acq ≈ 6.9ns. Additional time may be needed for amplifier settling and charge injection recovery.

Calculate theoretical SNR of a 12-bit ADC with 2V full scale.
SNR = 6.02N + 1.76 dB = 6.02(12) + 1.76 = 74.0 dB

This is the theoretical maximum SNR limited only by quantization noise, assuming a full-scale sinusoidal input. The full-scale voltage (2V) doesn’t affect this calculation — it’s purely a function of the number of bits. Real ADCs achieve lower SNR due to thermal noise, DNL/INL, clock jitter, etc.

ADC shows good DC performance but degrades at higher frequencies — three possible causes?
  1. Clock jitter (aperture jitter): Timing uncertainty in the sampling clock translates to amplitude noise. Impact scales with input frequency: SNR_jitter = −20·log(2πf_in·t_j).
  2. Bandwidth limitation of the sample-and-hold: Insufficient settling time at high frequencies causes incomplete acquisition, degrading SFDR and SINAD.
  3. Input buffer/driver bandwidth: If the ADC driver amplifier has insufficient bandwidth or slew rate, it distorts the signal before sampling. Also, the input network’s RC time constant may be too slow.
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