LDOs & Power Management

• Pass Element: Usually a P-channel MOSFET or PNP transistor that controls current flow from input to output.
• Error Amplifier: High-gain differential amplifier comparing feedback voltage to reference.
• Voltage Reference (V_ref): Typically a bandgap reference providing a stable, temperature-independent voltage.
• Resistor Divider: Scales the output voltage down for comparison with V_ref, setting the output voltage: V_out = V_ref(1 + R₁/R₂).

The LDO uses a negative feedback loop:

1. If V_out drops (increased load), V_fb at the error amplifier also drops.
2. The error amplifier senses V_fb < V_ref and drives the PMOS gate lower.
3. Lower gate voltage decreases R_ds(on), allowing more current to flow.
4. V_out rises back to the target setpoint.

The reverse happens if V_out rises: the error amplifier reduces drive to the pass element, restricting current.

• Dropout Voltage: Minimum V_in − V_out to maintain regulation.
• PSRR: Ability to reject input ripple/noise (dB vs. frequency).
• Quiescent Current (I_q): Current consumed by the LDO itself with no load.
• Load Regulation: ΔV_out for a change in load current.
• Line Regulation: ΔV_out for a change in input voltage.

Testing:

• Load regulation: Use an electronic load to step current from 0 to I_max, measure ΔV_out.
• Line regulation: Sweep V_in across its range and monitor V_out stability.

Feature	LDO (Linear)	SMPS (Switching)
Efficiency	Low — dissipates (V_in−V_out)×I as heat	High — often >90%
Output Noise	Very low, clean output	High — switching EMI/ripple
Complexity	Simple, few external parts	Complex — inductor, diode, control loop
Size	Small	Larger (inductor dominates)
Best For	Noise-sensitive analog, low current	High power, battery life critical

A bandgap reference sums two voltages with opposite temperature coefficients:

• V_BE: A diode junction voltage with a negative temperature coefficient (~−2mV/°C).
• ΔV_BE: The difference in V_BE between two transistors at different current densities, proportional to V_T = kT/q with a positive temperature coefficient.

By choosing the scaling factor K appropriately, the positive and negative temperature coefficients cancel, yielding a reference voltage near the silicon bandgap voltage (~1.12–1.25V) that is stable over temperature.

At low frequencies, the error amplifier’s high loop gain rejects supply noise. At high frequencies, PSRR degrades because:

• Error amplifier gain rolls off (finite GBW), reducing the loop’s ability to correct.
• The pass element’s gate capacitance and parasitics create feedthrough paths.
• Output capacitor ESR/ESL limits high-frequency filtering.

Improvements: Increase error amplifier bandwidth, add a cascode to the pass element for better isolation, use feed-forward ripple cancellation circuits, and add dedicated high-frequency decoupling at the output.

The V_out response shows an initial voltage dip followed by recovery:

1. Initial dip: Determined by the output capacitor — ΔV ≈ ΔI × ESR + ΔI·Δt/C_out. The ESR creates an instantaneous voltage step, and the capacitor discharge adds a ramp.
2. Recovery: The error amplifier detects the dip and increases pass element drive. Recovery time depends on loop bandwidth and phase margin.
3. Settling: Possible overshoot/ringing depending on loop stability (phase margin).

The voltage dip magnitude is dominated by C_out value and ESR for fast transients, and by loop bandwidth for slower transients.

Use multiple LDOs with separate regulators for analog and digital domains:

• Noise isolation: Digital switching noise won’t couple into sensitive analog blocks.
• Voltage optimization: Different blocks may need different voltages.
• Current management: Prevents one block’s transients from affecting another’s regulation.
• PSRR stacking: Each LDO adds its own power supply rejection.

Typical partition: separate LDOs for ADC analog, ADC digital, PLL/VCO, and general digital logic. Consider using a high-efficiency SMPS as a pre-regulator followed by LDOs for noise-sensitive rails.